Cadence Allegro and OrCAD.17.20.000-2016 HF027
Cadence Allegro and OrCAD 17.20.000-2016 HF027 | 1.6 Gb
Cadence Design Systems, Inc. has released an update (HF026) to OrCAD Capture, PSpice Designer and PCB Designer 17.20.000-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
Fixed CCRs: SPB 17.2 HF027 (09-29-2017)
CCRID Product ProductLevel2 Title
1795353 ADW FLOW_MGR Tool unable to find project in windows_project.txt
1810386 ADW FLOW_MGR Error regarding not finding project in 'windows_project.txt'
1743732 ADW LIBDISTRIBUTI adwserver -install does not give error if it cannot connect to server.
1804378 ALLEGRO_EDITOR 3D_CANVAS Bend area issues in 3D Viewer
1795312 ALLEGRO_EDITOR DATABASE Cannot unlock symbols as status is changed to View on opening design
1803262 ALLEGRO_EDITOR DATABASE Donut pad With DYN_THERMAL_CON set to FULL_CONTACT has connectivity issues
1802183 ALLEGRO_EDITOR DFM Using mouse wheel to scroll error information in DRC Browser changes font size
1797222 ALLEGRO_EDITOR DRC_CONSTR Updating DRC results in error 'SPMHDB-403'
1792163 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on moving components
1806640 ALLEGRO_EDITOR INTERFACES Step Mapping not working in release 17.2-2016 Hotfix 025
1807278 ALLEGRO_EDITOR INTERFACES Running 'step_export_product_asm.exe' displays 'vcruntime140.dll' missing error
1807286 ALLEGRO_EDITOR INTERFACES The facet file (.xml) for the STEP model 'modelname.step' cannot be found.
1808006 ALLEGRO_EDITOR INTERFACES Facet file for step model cannot be found
1704335 ALLEGRO_EDITOR MANUFACT Documentation Editor shows an error about backdrill while no backdrill was used in the design
1800115 ALLEGRO_EDITOR MANUFACT IPC2581 Export giving error that backdrill is out of date even though no backdrill is defined in the design
1799444 ALLEGRO_EDITOR PLACEMENT Via Array - Boundary placement fails with error
1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
1804129 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly
1805238 ALLEGRO_EDITOR SHAPE PCB Editor crashes while importing netlist
1803542 ALLEGRO_EDITOR SKILL Using axlPadstackEdit to change drill size causes via net to change in release 17.2-2016 Hotfix 025
1800774 APD STREAM_IF Only one pad in GDSII when running 'stream out' with the Flatten Geometry option
1804196 APD STREAM_IF Component is mirrored by X-axis instead of Y-axis on enabling mirror geometry
1803375 ASDA IMPORT_BLOCK Import HDL Block fails with message regarding Xnet states and DML independence
1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date
1789400 CAPTURE SCHEMATIC_EDI Capture schematic opens unannotated pages on search
1801573 CONCEPT_HDL CONSTRAINT_MG Upreving release 16.6 design to 17.2-2016 adds NO_XNET_CONNECTION to some components
1810586 CONCEPT_HDL CONSTRAINT_MG DE-HDL crashes when transferring XNET properties to similar components in a read-only block
1794169 CONCEPT_HDL CORE _automodel command crashes DE-HDL if PACK_IGNORE is set
1798672 CONCEPT_HDL CORE Dashes in design name creates an extra design folder in worklib after upreving to release 17.2-2016
1802258 CONCEPT_HDL CORE Locking unlocked components results in a warning (SPCOCN-3403)
1803019 CONCEPT_HDL CORE DE-HDL crashes on backannotation
1803615 CONCEPT_HDL CORE After running 'Mark for Variant', the block cannot be changed to blue
1804029 CONCEPT_HDL CORE Visibility issues when using the LOCK functionality
1806352 CONCEPT_HDL CORE Group Mirror is causing design corruption.
1806978 CONCEPT_HDL CORE Cannot mirror a group of objects
1810387 CONCEPT_HDL CORE Mirroring groups causes erratic display and may corrupt database if project is saved
1812811 CONCEPT_HDL CORE Schematic group mirror not working
1810401 CONCEPT_HDL INFRA Add Signal Name: Cannot select suggested net name
1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish
1800931 CONSTRAINT_MGR OTHER Even after removing NO_XNET_CONNECTION on parallel termination, topology extracted has duplicate capacitors
1790106 CONSTRAINT_MGR SCM Cannot find the constraints file (0) in the schematic project
1787117 CONSTRAINT_MGR UI_FORMS Creating bundle in Constraint Manager crashes PCB Editor
1797384 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read
1803226 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read
1664059 ORBITIO ALLEGRO_SIP_I Incorrect connectivity after .brd import
1799338 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC fails with internal memory error even after setting shape_cache_size
1799499 SIP_LAYOUT DRC_CONSTRAIN Multi-thread DRC fails
1806585 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC update aborted: internal memory resource depleted
1809804 SIP_LAYOUT DRC_CONSTRAIN Error message while updating DRCs in release 17.2-2016 Hotfix 026 regarding shape_cache_size
1788770 XTRACTIM ENG Translated bump / ball conductivity is wrong (PowerDC and XtractIM)
About Allegro and OrCAD 17.2-2016. The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
- OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
- New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.
- New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
- OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors' productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
- OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
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Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
- PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.
Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located
About Hot-Fix. A Hot-Fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack. Unlike Service Packs (SP), which are scheduled, periodic releases, Hot-Fix releases are not periodically scheduled. Simply requesting a Hot-Fix does not automatically guarantee that the customer will receive it: all Hot-Fix requests first must be approved and accepted by Cadence prior to delivery. Furthermore, a Hot-Fix may contain fixes related to problems reported earlier by different customers. All the files included in the Hot-Fix will nevertheless be installed.
About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF027
Supported Architectures: x64
Website Home Page :
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above
Size: 1.6 Gb
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